1. Field of the Invention
The present invention generally relates to a phase locked loop frequency synthesizer with automatic adjustment of a selected operating mode.
2. Description of the Related Art
A phase locked loop (PLL) frequency synthesizer is a circuit generating an output signal of a particular frequency that has a constant phase relationship to an input signal. The general configuration of a PLL frequency synthesizer is illustrated in the block diagram of FIG. 1. The PLL frequency synthesizer consists of a phase/frequency detector (PFD) 1, a low-pass filter 3 and a voltage controlled oscillator (VCO) 4. An input signal FIN is supplied to the phase/frequency detector 1 and the output signal FOUT of the VCO 4 is fed back to the phase/frequency detector 1. The phase/frequency detector 1 compares the phase of the input signal FIN to the phase of the feedback signal FOUT. If both signals differ from each other, the phase/frequency detector outputs an error signal indicating the magnitude of the difference. The error signal controls the VCO 4 in that the frequencies of both input signals (FIN, FOUTxe2x80x2) to the phase/frequency detector 1 finally match. The output signal (FOUT) of the VCO will be coupled to the phase of the input signal (FIN) when the phase difference falls below a particular error value.
The desired frequency of the VCO output signal FOUT is the frequency of the input signal FIN. The output frequency of the output signal FOUT may be a multiple of the frequency of the input signal FIN by employing a feedback divider 5. The above described PLL frequency synthesizer represents the particular case using a dividing value of N=1.
Due to the effect of the feedback path in the phase locked loop, the VCO output signal FOUT will have a fixed phase relationship with respect to the input signal FIN. The phases of the input and output signals will be synchronized with a minimal phase offset.
In many cases, a charge pump 2 is used to produce the tuning voltage for the VCO 4 based on the error signal output from the phase/frequency detector 1. A loop filter 3 connected between the charge pump and the VCO 4 is used to eliminate high frequency components from the VCO tuning voltage.
For low noise PLL applications, the loop gain of the VCO frequency control characteristic is one of the determining parameters. To achieve a low VCO phase noise, the PLL frequency synthesizer should have relatively low gain. In order to reduce the phase noise, VCOs are often designed by distributing the total operating frequency range on a plurality of operating frequency ranges. Such a VCO can reliably operate over a wide range of output frequencies using a relatively small VCO gain and a relatively small range of input voltages. The VCO is operated in one of a plurality of operating modes using a particular operating curve to generate an output frequency in response to the VCO input voltage. To achieve the desired PLL operation, that operating curve of the VCO has to be selected with the center frequency of the operating mode being close to the desired PLL output frequency.
A possible set of operating curves of a VCO is illustrated in FIG. 3. Each of the operating curves has a low gain and is operated by the same range of input voltages ranging from VMIN to VMAX. One of the operating curves S is selected at a time by a particular digital control word applied to the VCO.
Conventionally, the operating curve having the appropriate center frequency is selected when the PLL is powered up. During normal PLL operations, the loop filter voltage is applied to the VCO.
During a procedure of automatic selecting an appropriate operating curve, a reference voltage VREF is supplied to the VCO input rather than the loop filter voltage. The reference voltage VREF is preferably the nominal center of the range of input voltages over which the VCO is designated to operate. As illustrated in FIG. 2 showing a configuration of a corresponding PLL frequency synthesizer, switches 7 and 8 are opened and closed accordingly.
The operating curve is selected by a control word supplied from a self-calibration circuitry 6. The self-calibrating circuitry 6 receives the PLL input signal FIN and the PLL feedback signal FourOUT"". The self-calibrating circuitry 6 comprises a frequency detector 9 a digital accumulator 10 and a state machine 11. This circuitry is only operated during power up to select an appropriate operating curve by providing a code word to the VCO 4.
During self-calibration, the digital control word applied to the VCO is determined by incrementally increasing the digital control world until the measuring result of frequency detector 9 indicates that the desired optimal operating mode of the VCO is selected. Such a phase locked looped based frequency synthesizer is described by W. B. Wilson et al. in xe2x80x9cA CMOS self-calibrating frequency synthesizerxe2x80x9d in IEEE Journal Of Solid-State Circuits, vol. 35, no. Oct. 10, 2000.
PLL frequency synthesizers, and in particular VCOs, still have a number of problems. One problem is that an automatic selection of the appropriate operating range is only possible at power up. Any change of the desired output frequency during operation or any compensation of large drift or temperature deviations will not be possible without interrupting the frequency synthesizing operation.
An improved PLL frequency synthesizer is provided to enable an automatic adaptation to the operating range appropriate for a desired output frequency.
In one embodiment, a PLL frequency synthesizer is provided comprising a voltage controlled oscillator, a phase/frequency detector and an operating mode determining unit. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The phase/frequency detector generates an error signal based on a frequency input signal and a PLL feedback signal. The operating mode determining unit determines one of the operating modes of the voltage controlled oscillator based on the detected error signal. The operating mode determining unit includes a window comparator defining upper and lower error voltage limits for switching to adjacent operating modes when the error voltage exceeds or falls below the defined upper and lower voltage limits.
In a further embodiment, a method for controlling the operation of a voltage controlled oscillator in a PLL frequency synthesizer is provided. The voltage controlled oscillator is operable in a plurality of operating modes each of which defining a different operating frequency range of the voltage controlled oscillator. The method determines one of the operating modes of the voltage controlled oscillator based on an error signal between a frequency input signal and a PLL feedback signal. This determining step compares the error signal with predefined upper and lower error voltage limits for switching the current operating mode to an adjacent operating mode when the error signal exceeds or falls below the predefined upper or lower error voltage limits.
Further embodiments are the subject-matter of dependent claims.